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CXD2315Q
10-bit 80MSPS 1ch D/A Converter (Ultra-low Glitch Version)
Description The CXD2315Q is a 1-ch 10-bit 80MSPS D/A converter for monitor and video. This IC achieves high specifications for the industrial and information equipment due to the reduction of the glitch energy. Features * 10-bit resolution * Maximum conversion rate 80MSPS * Differential linearity error 0.5LSB * Low power consumption 150 mW (Max., When 80MSPS 200 load, 2 Vp-p is output) * Pin-compatible with CXD2306Q * Single 5 V power supply * Built-in independent constant-voltage source * Ultra-low glitch * Stand-by function Structure Silicon gate CMOS IC 32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 C) * Supply voltage AVDD, DVDD 7 V * Input voltage (All pins) VIN VDD +0.5 to VSS -0.5 V * Output voltage (for each channel) IOUT 0 to 15 mA * Storage temperature Tstg -55 to +150 C
Recommended Operating Conditions * Supply voltage AVDD, AVSS 5.0 0.25 DVDD, DVSS 5.0 0.25 * Reference input voltage VREF 0.5 to 2.0 * Clock pulse width tpw1, tpw0 5.6 (min.) * Operating temperature Topr -20 to +85
V V V ns C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E95704D01
CXD2315Q
Block Diagram
(LSB) D0 30 D1 31 D2 32 D3 D4 D5 D7 (MSB) D9 1 2 3 5 DECODER 19 VREF CURRENT CELLS (FOR FULL SCALE) CLOCK GENERATOR 17 IREF 21 AVDD BAND GAP REFERENCE 20 AVDD 18 SREF 7 DECODER 6MSB'S CURRENT CELLS LATCHES 23 IO 22 VG 4LSB'S CURRENT CELLS 24 IO 25 AVSS
D6 4 D8 6 DVDD 28 BLK 10 DVDD 13 DVSS 15 DVSS 27 CLK 9 VB 14 CE 11
BIAS VOLTAGE GENERATOR
Pin Configuration
VREF AVDD SREF
18
AVDD
VG
IO
IO
24
23
22
21
20
19
17
AVss 25 NC 26 DVss 27 DVDD 28 NC 29 D0 (LSB) 30 D1 31 D2 32
IREF
16 NC 15 DVss 14 VB 13 DVDD 12 NC 11 CE 10 BLK 9 CLK
1
2
3
4
5
6
7
8
D5
27 17
to 15 to 25
Digital section Analog section
--2--
D9 (MSB)
NC
D4
D3
D6
D7
D8
CXD2315Q
Pin Description and Equivalent Circuit Pin No. Symbol I/O Equivalent circuit
DVDD
Description
30 to 32 1 to 7
30
D0 to D9
I
to 7 DVSS
Digital input. 30 pin D0 (LSB) to 7 pin D9 (MSB)
8, 12, 16, 26, 29 9
NC CLK
--
10
BLK
I
9 10 11
DVDD
DVSS
11
CE
13, 28
DVDD
--
DVDD
No connection. Clock input. Blanking input. This is synchronized with the clock input signal. No signal (0 V output) at high and output state at low. Chip enable input. This is not synchronized with the clock input signal. No signal (0 V output) at high makes power consumption minimum. Digital power supply.
DVDD
14
VB
O
14
Connect a capacitor of approximately 0.1 F.
DVSS
15, 27
DVSS
--
AVDD AVDD
Digital ground. Reference current output. Connect resistance "RIR" which is 16 times output resistance "ROUT". Reference voltage input. Sets output full scale value. Connect a capacitor of approximately 0.1 F.
17
IREF
O
AVDD 17 AVss 19 AVSS 22 AVSS AVDD
19
VREF
I
22
VG
O
--3--
CXD2315Q
Pin No.
Symbol
I/O
Equivalent circuit
AVDD
Description Independent constant-voltage source output pin using band gap reference. Stable voltage independent of the fluctuation for supply voltage can be get by connecting to VREF. See Application Circuit 2 for details.
18
18
SREF
O
AVSS
AVSS
20, 21
AVDD
--
Analog VDD
23
IO
24 AVSS
Inverted current output. Connect to GND normally.
O
23
24
IO
AVSS
Current output. Output can be retrieved by connecting resistance. The standard is 200 . Analog ground.
25
AVSS
--
--4--
CXD2315Q
Electrical Characteristics Item Resolution Conversion speed Integral non-linearity error Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage Output full-scale current Output offset voltage Glitch energy Differential gain Differential phase Supply current Analog input resistance Input capacitance Digital input voltage Digital input current SREF output voltage Setup time Hold time Rise time Propagation delay time CE enable time CE disable time
(FCLK=80 MHz, AVDD=DVDD=5 V, ROUT=200 , RIR=3.3 k, VREF=2.0 V, Ta=25 C) Symbol n FCLK EL ED VOC VFS IFS VOS GE DG DP IDD ISTB RIN CI VIH VIL IIH IIL VSR ts th tr tPD tE tD Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +85 C Endpoint Min. Typ. 10 Max. Unit bit MSPS LSB LSB V V mA mV pV*s % deg mA M pF V A V ns ns ns ns ms ms
0 -1.5 -0.5 1.8 1.8 9.0 1.94 1.94 9.7
80 1.5 0.5 2.0 2.0 10 1 30 1.0 1.0 30 1 9
When D0 to D9= "0000000000" input
CE= "L" CE= "H" VREF AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C AVDD=DVDD=4.75 to 5.25 V Ta=-20 to +75 C
1 2.45 0.85 -5 1.0 3.0 3.0 5 1.2 5 1.45
CE= HL CE= LH
5 1 1
2 2
When the external capacitor for the VGR,VGG and VGB pins are 0.1 F. Electrical Characteristics Measurement Circuit Analog Input Resistance Measurement Circuit Digital Input Current
}
+5.25V
AVDD, DVDD
A
CXD2315Q
V
AVSS, DVSS
--5--
CXD2315Q
Maximum Conversion Rate Measurement Circuit
10bit COUNTER with LATCH
30 D0 (LSB) 31
IO 24 0.1 AVDD 200
OSCILLOSCOPE
7 D9 (MSB) 9 CLK 10 BLK
VG 22 2V 5k AVss IREF 17 3.3k
VREF 19
CLK 80MHz (max) SQUARE WAVE
11 CE 14 VB 0.1
DC Characteristics Measurement Circuit
30 D0 (LSB) CONTROLLER 31
IO 24 0.1 AVDD 200
DVM
7 D9 (MSB) 9 CLK 10 BLK CLK 80MHz SQUARE WAVE 11 CE 14 VB 0.1
VG 22 2V 5k AVss IREF 17 3.3k
VREF 19
Propagation Delay Time Measurement Circuit
30 D0 (LSB) 31 0.1 7 D9 (MSB) FREQUENCY DEMULTIPLIER CLK 10MHz SQUARE WAVE 9 CLK 10 BLK 11 CE 14 VB 0.1 VG 22 2V 5k AVss IREF 17 3.3k AVDD IO 24 200 OSCILLOSCOPE
VREF 19
Setup Time Hold Time Glitch Energy
}
Measurement Circuit
10bit COUNTER with LATCH
30 D0 (LSB) 31
IO 24 0.1 AVDD 200 OSCILLOSCOPE
7 D9 (MSB) 9 CLK 10 BLK 11 CE 14 VB 0.1
VG 22 2V 5k AVss IREF 17 3.3k
DELAY CONTROLLER CLK 1MHz SQUARE WAVE DELAY CONTROLLER
VREF 19
--6--
CXD2315Q
Description of Operation Timing Chart
tPW1 tPW0
CLK 1.5V ts th ts th ts th
DATA
tPD
100%
D/A OUT
50%
tPD
tPD
0%
I/O Correspondence Table (When 2.00 V output full-scale voltage) Input code MSB LSB 1111111111 : 1000000000 : 0000000000 Output voltage 2.0 V 1.0 V 0V
--7--
CXD2315Q
Application Circuit 1
R3
AVDD
DVDD
R4 R1 C R2 C 24 IO 25 AVss 23 IO 22 VG 21 AVDD 20 AVDD 19 VREF 18 17 AVSS DVSS
SREF IREF NC 16
26 NC
DVss 15
27 DVss
VB 14 C
28 DVDD C 29 NC
DVDD 13
NC 12
30 D0
CE 11
31 D1
BLK 10
32 D2 D3 1 D4 2 D5 3 D6 4 D7 5 D8 6 D9 7
CLK 9 NC 8
Clock input
* When 5.0V supply voltage (DVDD and AVDD) * Digital input from Pins 30 to 32 and Pins 1 to 7 * Pin 18 is left open when using normally * R1=200 * R2=3.3k (resistance 16 times R1) (RIR) * R3=3.0k * R4=2.0k * C=0.1F
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--8--
CXD2315Q
Application Circuit 2
AVDD
DVDD
R1
C
Cr R2
AVSS
DVSS
C 24 IO 25 AVss 23 IO 22 VG 21 AVDD 20 AVDD 19 VREF 18 SREF 17 IREF NC 16
26 NC
DVss 15
27 DVss
VB 14 C
28 DVDD C 29 NC
DVDD 13
NC 12
30 D0
CE 11
31 D1
BLK 10 CLK 9 NC 8
32 D2 D3 1 D4 2 D5 3 D6 4 D7 5 D8 6 D9 7
Clock input
* When 5.0V supply voltage (DVDD and AVDD) * Digital input from Pins 30 to 32 and Pins 1 to 7 * R1=200 * R2=2.0k * C =0.1F * Cr =4.7F
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--9--
CXD2315Q
Notes on Operation * Selecting the Output Resistance CXD2315Q is a current output type D/A converter. To create the output voltage, connect the resistor to the current output pin IO. Specifications: Output full-scale voltage VFS = 1.8 to 2.0 [V] Output full-scale current IFS = 10 or less [mA] Calculate the output resistance from VFS = IFS x ROUT. Connect a resistance sixteen times the output resistance to the reference current pin IREF. In some cases, as this value may not exist, a similar value can be used instead. Note that the VFS will be the following. VFS = VREF x 16 ROUT/R VREF is the voltage set at the VREF pin, ROUT is the resistor to be connected to the current output pin IO and RIR is the resistor to be connected to the IREF. Power consumption can be reduced by increasing the resistance, but this will on the contrary increase the glitch energy and data settling time. Set the best values according to the purpose of use. * Correlation between Data and Clock For the CXD2315Q to display the desired performance as a D/A converter, the data transmitted from outside and the clock must be synchronized properly. Adjust the setup time (ts) and hold time (th) as specified in "Electrical Characteristics". * Power supply and ground Separate the analog and digital power supplies and grounds around the device to reduce noise effects. Bypass the power supply pin to each ground with a 0.1 F ceramics capacitor as near to the pin as possible for both the digital and analog signals. * Latch up Analog and digital power supply must be able to share the same power supply of the board. This is to prevent latch up caused by potential difference between the two pins when the power is turned on. * IREF pin The IREF pin is very sensitive to improve the AC characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable. * VG pin It is recommended to use a 1 F capacitor to improve the AC characteristics though the typical capacitance value externally connected to the VG pin is 0.1 F. * SREF SREF is an independent regulated voltage source. By connecting the SREF pin and the VREF pin, stable output amplitudes that do not depend on fluctuations in the power supply can be obtained. In this case, as described above, VFS = VSR x 16ROUT/RIR, set the VFS according to RIR. VSR is the output voltage of the SREF pin. Do not use this pin as a reference power supply for other ICs because this is dedicated for the VG pin of the CXD2315Q. --10--
CXD2315Q
* IO pin The IO pin is the inverted current output pin described in the Pin Description. The sum of the currents output from the IO pin and the IO pin becomes the constant value for any input data. However, the performances such as the linearity error of the IO pin output current is not guaranteed. GE (Glitch energy) GE, described in the CXD2315Q, is a spike noise which appears synchronizing with the clock falling edge when the input data (for 1 to 1024 input) changes to 128, 256, 384, 512, 640, 768, 896, and 1024. Fig. 1 shows the change state of GE for the staircase wave output, and Fig. 2 shows the repetitive output waveform where the GE appears. These figures exhibit the difference of this IC from the conventional device.
2.0
Analog output [V]
Conventional device 1.0
CXD2315Q
0
512 Digital input [V]
1024 CLK
Fig. 1. Change of GE for staircase wave output
Conventional device (GE typ.=200pV-s)
CXD2315Q (GE typ.=10pV-s)
Fig. 2. Repetitive output waveform where GE appears (for 200 , 2 Vp-p output) The CXD2315Q reduces the GE much shown in Fig.s 1 and 2. --11--
CXD2315Q
Latch Up Prevention The CXD2315Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in the voltage rising time of AVDD (Pins 20 and 21) and DVDD (Pins 13 and 28), when power supply is ON. 1. Correct usage a. When analog and digital supplies are from different sources
DVDD AVDD
20
21
13
28
AVDD +5V +5V C CXD2315Q
DVDD C DIGITAL IC
AVSS AVSS 25
DVSS 15 DVSS 27
b. When analog and digital supplies are from a common source (i)
DVDD
20
21
13
28
AVDD +5V C CXD2315Q
DVDD C DIGITAL IC
AVSS AVSS 25
DVSS 15 DVSS 27
(ii)
DVDD
20
21
13 28 DVDD C
AVDD +5V C CXD2315Q
DIGITAL IC
AVSS 25 AVSS DVSS
DVSS 15 27
--12--
CXD2315Q
2. Example when latch up easily occurs a. When analog and digital supplies are from different sources
DVDD AVDD 20 21 13 28
AVDD +5V +5V C CXD2315Q
DVDD C DIGITAL IC
AVSS AVSS 25
DVSS 15 DVSS 27
b. When analog and digital supplies are from common source (i)
DVDD AVDD 20 21 13 28 DVDD CXD2315Q C DIGITAL IC
AVDD +5V C
AVSS AVSS 25 DVSS
DVSS 15 27
(ii)
DVDD AVDD 20 21 13 28
AVDD +5V CXD2315Q
DVDD C DIGITAL IC
AVSS AVSS 25
DVSS 15 DVSS 27
--13--
CXD2315Q
Example of Representative Characteristics
Output full-scale voltage VFS [V]
Output full-scale voltage VFS [V]
2.0
1.95
1.0
1.93
V = 0.20mV/C 0 1.0 2.0 0 -25 0 25 50 75
Reference voltage VREF [V] Fig. 3. Reference voltage vs.Output full-scale voltage
Ambient temperature Ta [C] Fig. 4. Ambient temperature vs. Output full-scale voltage
SREF Output voltage VSR [V]
1.25
30
Supply current IDD [mA]
V = -0.7mV/C
1.15
20
0
-25
0
25
50
75
0
1
10
20
30
40
Ambient temperature Ta [C] Fig. 5. Ambient temperature vs. SREF output voltage
Output frequency Fo [MHz] Fig. 6. Output frequency vs. Supply current
Standard Measurement Conditions and Description * ADDD=DVDD=5V * VREF=2.0V * ROUT=200 * RIR=3.3k * FCLK=80MHz * Ta=25C * Fig. 4 includes the temperature characteristics of external metal film resistor. * Input data in Fig. 6=all "0" and "1" of rectangular wave; clock frequency=80MHz.
--14--
CXD2315Q
Package Outline
Unit : mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.24
M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
--15--
0.50
(8.0)

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